Semiconductor devices such as power MOSFETs often contain electrostatic discharge (ESD) protection circuits that protect the devices from damage that ESD can cause. FIG. 1A shows a circuit diagram for a semiconductor device 100 having ESD protection. Device 100 includes a MOS (metal-oxide-semiconductor) field effect transistor (MOSFET) 107. A bonding pad 101 (sometimes referred to herein as a gate pad), a bonding pad 102 (sometimes referred to herein as a source pad), and a bonding pad 103 (sometimes referred to herein as a drain pad) are respectively connected to the gate, source, and drain of MOSFET 107. In some cases (as in a vertical power MOSFET), the drain pad 105 is actually the backside of the wafer whereby the “pad” indicates an external connection, but not necessarily a bonding pad, perse. A PN junction diode 108 naturally present between drain pad 103 and source pad 102 in MOSFET 107 protects against high drain-to-source voltage that could damage junctions in MOSFET 107. For ESD protection of the gate insulator in MOSFET 107, device 100 has back-to-back zener diodes 104 and 105 connected in series between gate pad 101 and source pad 102, and series gate resistor 106 representing series resistance R1 between gate pad 101 and the gate electrode contained within MOSFET 107. Unlike the protection needed between gate and source pads, no ESD diode is needed between drain pad 103 and gate pad 101 because of MOS capacitor effects that cause depletion in the silicon and low electric field across the gate oxide, even at high applied voltages.
FIG. 1B shows an ideal plot of the current IG through gate pad 101 as a function of the voltage VGS between gate pad 101 and source pad 102. In the normal operating range of voltage VGS, current IG is ideally zero since a gate oxide layer insulates the gate of MOSFET 107 (preventing DC current flow from the gate) and since one of the two diodes of back-to-back pair 104 (D1) and 105 (D2) remain reverse-biased below their avalanche breakdown voltage (hence no diode current except for junction leakage should flow). Diode 104 breaks down when voltage VGS reaches the positive breakdown voltage BVD1 and prevents the voltage across the gate oxide in MOSFET 107 from reaching a large positive voltage that could damage the gate oxide. Similarly, diode 105 breaks down when gate-to-source voltage VGS reaches the negative breakdown voltage −BVD2 and prevents the voltage across the gate oxide from reaching a large negative value that could damage the gate oxide.
An actual device generally cannot achieve the ideal current-voltage plot of FIG. 1B because of current leakage through the gate oxide of MOSFET 107 and through diodes 104 and 105. A resistive element 106 having a resistance R1 improves the ESD protection of the gate oxide by limiting the maximum gate voltage during an ESD transient. The reduction in maximum gate voltage is achieved by slowing down the gate's voltage rise through an increase in the RC time constant of the gate-capacitance/gate-resistor network.
FIG. 1C is a cross-sectional view of an example of a semiconductor structure 120 using a vertical planar DMOS transistor for one implementation of device 100 of FIG. 1A. Semiconductor structure 120 is fabricated in and on an N++ substrate 123 having an N-type epitaxial layer 122. The vertical planar DMOS comprises a vertical current flow device with a topside source and gate connection and a backside drain connection (hence the nomenclature “vertical”). The drain pad or contact is at the bottom of N++ substrate 123. The planar DMOS is referred to as planar since the MOS action of the gate electrode occurs on the top, i.e. planar, surface of epitaxial layer 122 atop P-type body PB 121A, 121B, and 121C.
For ESD protection, back-to-back zener diodes D1 and D2 between the source and gate pads are formed using an N-type region 131, a P-type region 132, and an N-type region 133 that are adjacent portions of a polysilicon layer overlying a field oxide region 134. Through openings in a patterned insulating layer 128, a patterned metal region 129 connects the source pad (not shown) to N-type region 131 and to N+ source regions 124A, 124B, and 124C and P+ body contact regions 125A and 125B. P+ body contact regions 125A and 125B are in respective deep P-wells 127A and 127B, and the junctions between deep P-wells 127A and 127B and epitaxial layer 122 form a diode (e.g., diode 108) between the drain and source contacts.
The gate pad electrically connects to polysilicon gate regions 126A and 126B in a portion of semiconductor structure 120 not shown in FIG. 1C. Gates 126A and 126B overlie horizontal channel regions 121A, 121B, and 121C that are in P-type body regions 121A, 121B, and 121C and adjacent to respective source regions 124A, 124B, and 124C. Gates 126A and 126B also overlie portions of N-type epitaxial layer 122 that form respective drain regions. The gate pad through a metal region 130 also electrically connects to N-type polysilicon region 133, that with adjacent P-type polysilicon region 132 and N-type polysilicon region 131 forms the back-to-back zener diodes D1 and D2.
FIG. 1D is a cross-sectional view of an example of a semiconductor structure 140 using vertical transistor cells for another implementation of device 100 of FIG. 1A. As in semiconductor structure 120, semiconductor structure 140 is fabricated in and on an N++ substrate 146 having an N-type epitaxial layer 145, and the drain pad is at the bottom of N++ substrate 146.
In structure 140, an N-type region 148, a P-type region 149, and an N-type region 149, which are formed in a polysilicon layer overlying insulating layers 150 and 151, form the back-to-back zener diodes D1 and D2 for ESD protection. The source pad is connected to a patterned metal region 153 that contacts N-type region 148, N+ source regions 142A, 142B, and 142C, and P+ body contact region 143. The contacts between metal region 153 and regions 142A, 142B, 142C, and 143 can be formed in a traditional manner through openings formed during a masked etching of an insulating layer or alternatively formed using a super self aligned process such as described in U.S. Pat. No. 6,413,822, which is hereby incorporated by reference in its entirety. P+ body contact region 143 is in a P-type body 141 that also includes vertical channel regions 141A, 141B, and 141C. A junction between P-type body 141 and epitaxial layer 145 forms the diode between the drain and source pads.
The gate pad electrically connects to polysilicon gate regions 143A to 143D that are in trenches that extend through P-type body 141 into epitaxial layer 145. Oxide 144 in the trenches isolates gate regions 143A to 143D from channel regions 141A, 141B, and 141C at the vertical walls of the trenches. The gate pad via a metal region 154 also electrically connects to N-type polysilicon region 150 that with P-type polysilicon region 149 and N-type polysilicon region 148 forms back-to-back zener diodes D1 and D2 between the gate and source pads.
FIG. 1E shows a circuit diagram for another known device 200 having ESD protection circuitry. Device 200 is similar to device 100 of FIG. 1A but differs from device 100 in the addition of a second pair of back-to-back zener diodes 206 and 207. In device 200, resistive element 106 is between gate pad 101 and diode 206 and between diode 104 and diode 206. Accordingly, during an ESD event, more of the current flowing into gate pad 101 flows through diodes 104 and 105 than through diodes 206 and 207. The ESD current and voltage spike is thus kept further from the gate of MOSFET 107, with resistor 106 (R1) aiding in the division of current during an ESD transient. Device 200 can be implemented using structures similar to those of FIG. 1C or 1D.
FIGS. 2A and 2B show typical plots of the current IG through the gate pad of a power MOSFET with ESD protecting diode, where the y-axis for current IG of the graph is logarithmic in FIG. 2A and linear in FIG. 2B. FIG. 2A shows a plot 220 illustrating the room temperature leakage current for voltage VGS between the breakdown voltages BV1 and −BV2 of the back-to-back diodes. Shown on a log scale, the leakage current in the polysilicon diode increases rapidly at small biases, then at larger voltages the leakage saturates until breakdown is reached, whereupon a dramatic increase in current is manifest. The leakage of the gate dielectric itself is orders of magnitude less than leakage through the polysilicon diodes, so leakage through the gate dielectric has no influence on the device's gate terminal I-V characteristics. FIG. 2B shows a linear-scale plot 230 of current IG versus voltage VGS when the power transistor operates at a lower temperature (e.g., room temperature) and a plot 231 of current IG verses voltage VGS when the power transistor operates at a higher temperature. As shown in FIG. 2B, a temperature increase generally increases the leakage current and can change breakdown voltages of one or more of the diodes in the ESD protection circuitry.
Under certain conditions, the gate-to-source voltage VGS used in operating a power MOSFET is also known to affect the useful life of the power MOSFET. FIG. 2C shows curves 240 and 241 illustrating the useful lifetimes t3 and t4 of good power MOSFETs respectively operated at gate voltages VG1 and VG2. Of course, operating lifetime is a matter of population statistics requiring many units to discern a difference in lifetime failures (also known as end-of-life or old-age failures). In this statistical context, a good power MOSFET may have a shorter life t3 at the higher gate voltage VG2, than the power MOSFET would if biased at a lower gate bias but the lifetime t3 is still commercially valuable (e.g., more than 20 years). The specific failure mechanism is due to the acceleration of charges damaging or dislocating atoms in the oxide matrix. Failure rates increase in relation to increased electric fields across the gate dielectric (i.e., VG/Xxo, where Xox is the gate oxide thickness). Plots 242 and 243 show that operating defective power MOSFETs at gate voltages VG1 and VG2 provides lifetimes t1 and t2 that are only days or weeks long, which is commercially unacceptable. Moreover it can be seen that for the same degree of defectivity, the devices operating at higher gate biases (and higher corresponding electric fields) fail first. In general, silicon dioxide formed in a defect free manner exhibits a useful life of more than 20 years as long as it is operated at maximum electric fields less than or equal to about 4 MV/cm. Defective material however may fail in one quarter their normal use life even at low bias conditions.
An ESD event can also shorten the life of a power MOSFET by creating or exacerbating damage in a dielectric, particularly if the power MOSFET has a latent gate oxide defect or weak spot. As illustrated in FIG. 2D, if an ESD event can be avoided, a power MOSFET with a latent defect can be expected to have a lifetime t3 of weeks, months and even a few years, while a good power MOSFET has a useful life that may be more than 20 years. If an ESD event occurs, a good power MOSFET that is adequately protected from ESD may have its life shortened somewhat, but the good power MOSFET will still generally have a useful lifetime t4 that is more than 15 to 20 years. Adequate protection in this context generally means that the maximum voltage electric field strength in the gate insulator does not exceed 8 MV/cm or if the voltage electric field does exceed this value, the pulse duration is held to a very short duration by the ESD protection elements. Short (sub-nanosecond) duration pulses do minimal damage to the oxide since a short pulse contains only a limited amount of energy. If an ESD occurs and the ESD protection circuit is defective or inadequate, a power MOSFET having a latent gate oxide defect may fail almost immediately at time t0 after the ESD, although the defective power MOSFET could last for weeks or months of operation before failing catastrophically. If the ESD protection fails or is inadequate, even a good power MOSFET may prematurely fail in a short time t1 (e.g., immediately or days-to-months) later.
FIG. 2E is a histogram illustrating the premature failure rate for power MOSFETs at different electric field strengths in the gate oxides of the power MOSFETs. As illustrated, the defective power MOSFETs prematurely fail at low gate-to-source electric fields VGS (e.g., 3 MV/cm), while good power MOSFETs prematurely fail only at much higher voltages VGS (e.g., around 8 to 10 MV/cm).
Ideally, a test process for a power MOSFET would identify all power MOSFETs having latent gate oxide defects and remove them so that all defective power MOSFET can be removed from the population. As shown in plot 251 of FIG. 3, a stress test applying a gate voltage corresponding to an electric field of 4 MV/cm, just above the voltage and field (e.g., 3 MV/cm) that causes premature failure in defective power MOSFETs will cause the defective power MOSFETs to fail but may take a time t1 measured in days or weeks to separate all or most defective MOSFETs from the good MOSFETs. Test times of this length are expensive and generally not commercially practical. Plot 250 shows that a higher test voltage (e.g., 6 MV/cm) can cause a rapid failure of the defective MOSFETs and provide shorter test times allowing bad parts to be screened and pruned from the population. Unfortunately, adequate ESD protection circuits, which are necessary to prevent ESD-induced failures of good devices, may not allow testing at high enough gate voltages to identify defective devices in a reasonable amount of time. In essence, the ESD protection devices and networks included to protect in a power MOSFET actually prevents the testing of devices to remove defective components from the population.
Circuits and fabrication processes are thus needed that provide ESD protection that can be tested for operability and not interfere with the normal operation of the device. Further, the ESD protection must be adequate to prevent premature failure of good devices while still permitting stress tests that detect defective devices within a commercially efficient testing time.